1. Field of the Invention
The present invention generally relates to a normally-off type MOS (metal oxide semiconductor) device. More specifically, the present invention is directed to a MOSFET having a low ON-resistance with a short channel formed in a depth direction thereof.
2. Description of the Related Art
Various types of MOS devices have been described in the semiconductor field, for instance, "MODERN POWER DEVICES" written by B. J. Baliga issued by J. Wiley & Sons Inc. New York, on page 236.
FIG. 1 is a sectional view of the conventional DMOS structure semiconductor device as described in the above-described publication. In the DMOS structure semiconductor device shown in FIG. 1, reference numeral 1 indicates an n-type drain, reference numeral 11 denotes a drain electrode; reference numeral 2 represents a p type base region; reference numeral 22 is a p.sup.+ type region for a contact of the base region; reference numeral 3 indicates an n.sup.+ type source region; reference numeral 33 represents a source electrode; reference numeral 4 is a gate electrode; reference numeral 5 denotes a gate insulating film; reference numeral 6 indicates an interlayer insulating film; symbol "C" indicates a channel; and also symbols "L" represents a length of this channel. It should be understood that the drain region 1 is in ohmic-contact with the drain electrode 11.
A structure of a typical lateral type MOSFET is so arranged that a plurality of unit structures, as represented in FIG. 1, are positioned in parallel with each other on a surface of the same semiconductor chip.
Operations of the conventional MOSFET shown in FIG. 1 will now be described.
It should be noted that the drain electrode 11 is biased at a positive potential and the source electrode 33 is grounded.
When the potential of the gate electrode 4 is equal to that of the source electrode 33, i.e., ground potential, no current flows between the source region 3 and drain region 1, because the path between these regions 1 and 3 is electrically cut off due to existence of the p type base region 2. Then, when a predetermined positive potential is applied to the gate electrode 4, an inversion layer is formed at the surface of the gate insulating film 5 adjacent to the p type base region 2 and this inversion layer functions as the channel "C", so that since the source region is electrically connected to the drain region, the main current flows therethrough.
In general, it is known that a so-called "ON-resistance", namely a resistance of a semiconductor device per se when it is under ON-state should be lowered as much as possible. In the above-described structure of the conventional MOS device, "a channel resistance" caused when the current flows through the inversion layer functioning as the channel, may give a major effect to the ON-resistance. The shorter, the channel length "L" is designed, the lower the channel resistance becomes, and also the smaller the dimension of the structure unit shown in FIG. 1 becomes. As a result, the current capacity per unit region may be increased. However, there is such a limitation that if the channel length "L" is made too short, the withstanding voltage characteristic of this device will be lowered. That is to say, the channel length is restricted to the allowable value which is determined by the breakdown voltage characteristic and threshold voltage.
Also, there is another problem in this MOS structure. That is, an npn bipolar transistor constructed of the drain region 1, base region 2 to source region 3 is present as a stray device. When a drain voltage with a rapid change is applied to this device, the stray transistor may function and thus the MOS device per se is broken.
Another typical MOS structure with a so-called "UMOS structure" is described in, for example, Japanese Laid-open Patent Application No. 58-63130.
In this known UMOS structure, the channel is formed in the depth direction of this structure so as to improve the density of the structure unit in such a manner that the insulating gate is formed in the groove which has been vertically dug from the surface of the semiconductor substrate and has a U shape, and the channel is formed on the side walls of this U-shaped groove.
In FIG. 2, there is shown the above-described UMOS structure as a sectional view. It should be noted that the same reference numerals shown in FIG. 1 will be employed for denoting the same or similar elements in FIG. 2.
As shown in FIG. 2, since the channel is formed in the lateral direction of this UMOS device, the dimension of the UMOS structure unit may be considerably reduced even with the same channel length as that of the MOS device shown in FIG. 1. As a result, although the ON-resistance of this UMOS structure become lower, there are still same problems as those of the first-mentioned MOS structure, namely the breakdown voltage and stray transistor matters.
As a MOS device with a shorter channel length, a static induction transistor (SIT) is well known in the art, for instance, from the above-described publication "MODERN POWER DEVICES" on page 182, in which both the junction gate and insulating gate have been proposed as the gate structure.
A static induction transistor does not employ an opposite conductivity type impurity region as a channel structure so that there is no stray device and ON-resistance is low, because the major current does not flow through a narrow region such as an inversion layer. On the other hand, the general vertical MOSFET structure which is applied no gate voltage can block the main current (normally-off) until the drain voltage increases to the breakdown voltage, but for static induction transistor, the opposite polarity voltage to that of the drain electrode must be applied to the gate electrode to block the main current. Even if such a structure capable of cutting the flow of the main current is realized under the grounded gate electrode, the main current will start to flow in accordance with an increase in the drain voltage, since the static induction transistor originally represents a triode characteristic, which may cause a difficult device treatment.
As previously described in detail, the conventional DMOS and UMOS devices own the following drawbacks. That is to say, there is a limitation in shortening the channel length because of the breakdown voltage and threshold voltage. As a consequence, it is rather difficult to reduce the channel resistance mainly functioning as the ON-resistance. Furthermore, there is a risk that these devices per se are broken down due to the existence of such an inherent stray transistor.
Moreover, the voltage having the polarity opposite to that of the drain electrode must be applied to the gate electrode of the static induction transistor in order to interrupt the flow of the main current. Since the static induction transistor represents the triode characteristic, the main current may start to flow in response to an increase of the drain voltage. Therefore, it is difficult to handle such a static induction transistor with satisfaction.